Latch-up is a general problem associated with CMOS structure that induces an undesirable conduction mechanism. CMOS integrated circuits include parasitic P/N/P/N structures that have the latch-up problem when one of the junctions in the P/N/P/N structures is forward biased. A guard ring structure and/or a pick-up structure are applied to the CMOS integrated circuits to prevent the latch-up problem, but the guard ring structure and/or the pick-up structure consume large layout area.